//FileName   : dmem
//Author     : -
//Description: dmem
//ModifyDate : 2019-5-8
//Company    : -
//Copy right : -


module dmem (
    input               clk,
    input               rst_n,
    input     [9:0]     dmem_adr,
    input               dmem_cs,
    input               dmem_we,
    input     [7:0]     dmem_wdat,
    output     [7:0]    dmem_rdat,
    output reg          dmem_ack
);

//internal wire define

//internal temp define
reg [9:0]     dmem_adr_d1;

//memory define
reg [7:0]     mem[0:1023];



//---------------------------------------------
//Function: AA
//---------------------------------------------

always @(posedge clk)
begin
    if(dmem_cs& dmem_we)
        mem[dmem_adr] <= dmem_wdat;
end

always @(posedge clk)
begin
    if(!rst_n)
        dmem_adr_d1 <= 10'd0;
    else begin
        dmem_adr_d1 <= dmem_adr;
    end
end

assign dmem_rdat = mem[dmem_adr_d1];

always @(posedge clk)
begin
    if(!rst_n)
        dmem_ack <= 1'd0;
    else begin
        dmem_ack <= dmem_cs;
    end
end

endmodule
